1. Field of the Invention
The invention relates generally to semiconductor circuit devices for decoding a multibit input signal and selectively activating a plurality of subsequent stage circuits in accordance with the result of the decoding and activating methods thereof. More particularly, the invention relates to semiconductor memory devices having a decoder circuit for selecting a row or a column of a memory cell array in response to an external address.
The invention further relates to an improvement of a defective circuit repairing scheme in a semiconductor circuit device having a defective circuit repairing function.
2. Description of the Background Art
As one typical example of a semiconductor circuit device having a function of selectively activating a plurality of subsequent stage circuits, a semiconductor memory device will now be described by way of example.
FIG. 1 is a diagram schematically showing the whole structure of a conventional semiconductor memory device. In FIG. 1, the semiconductor memory device includes a memory cell array 1 in which memory cells each for storing information are arranged in a matrix of rows and columns. In order to select a row and a column respectively from this memory cell array 1, there are provided a row address buffer 2 for receiving an externally applied row address and generating an internal row address RA, a row decoder 3 for decoding the internal row address RA and selecting a corresponding row in the memory cell array 1, a column address buffer 4 for receiving an externally applied column address and generating an internal column address CA, and a column decoder 5 for decoding the internal column address CA and selecting a corresponding column in the memory cell array 1.
A (sense amplifier+I/O) block 6 and an input/output circuit 7 are provided for transmitting and receiving data between a memory cell designated by a row address and a column address, and an outside of the memory device. The sense amplifier of the (sense amplifier+I/O) block 6 senses and amplifies the data of a selected memory cell. The I/O in this block 6 connects a designated column to common data lines (not shown) corresponding to a column select signal from the column decoder 5. The selected column is thereby connected to the input/output circuit 7 over the common data lines.
The input/output circuit 7 derives external data D in response to the data amplified by the sense amplifier in the (sense amplifier+I/O) block 6 at the time of reading data. The input/output circuit 7 generates internal data corresponding to an externally applied data D and supplies the same to the I/O of the block 6 over the common data lines at the time of writing data.
In the structure of the semiconductor memory device shown in FIG. 1, a row address and a column address are supplied in parallel to the row address buffer 2 and the column address buffer 4.
FIG. 2 is a diagram schematically showing the structure of the memory cell array 1 shown in FIG. 1. In FIG. 2, the structure of the memory cell array is shown as an example where the semiconductor memory device is a static type semiconductor memory device. This semiconductor memory device, however, may be a dynamic type semiconductor memory device or a read only memory capable of reading data only.
In FIG. 2, there are representatively shown three word lines WL1 to WL3, and three pairs of bit lines BL0, *BL0, BL1, *BL1, and BL2, *BL2. Memory cells MC10, MC11, MC12, MC20, MC21 and MC22 are provided respectively at crossing points of each of the word lines WL1 to WL2 and the bit line pairs BL0, *BL0, BL1, *BL1 and BL2, *BL2.
One row of memory cells is connected to one word line and one column of memory cells is arranged in one pair of bit lines. Each of the bit line pairs BL0, *BL0, BL1, *BL1, and BL2, *BL2 forms a complementary signal line pair and signals complementary to each other are transmitted to the bit line BL (BL0 to BL2) and the bit line *BL (*BL0 to *BL2).
By selecting one word line and then a pair of bit lines, a memory cell located at the crossing point thereof is selected.
FIG. 3 is a diagram schematically showing the structures of the column decoder and the (sense amplifier +I/O) block shown in FIG. 1. In FIG. 3, the sense amplifier included in the block 6 is omitted.
In FIG. 3, the column decoder 5 includes (m+1) decoder circuits 8-0 to 8-m. Each of the decoder circuits 8-0 to 8-m includes an AND circuit and each receives a predetermined combination of internal column address bits. The decoder circuits 8-0 to 8-m generate a column select signal Y0 to Ym when the predetermined applied predetermined internal column address bits applied thereto all attain "H" of an activate state, where the term "generate" means to bring a select signal to an active state.
In the structure shown in FIG. 3, two columns are selected at the same time, so that a column select signal generated from one decoder circuit selects adjacent two pairs of bit lines.
More precisely, a column select signal from the decoder circuit is supplied to the gate of an I/O gate transistor provided for each bit line pair. I/O gate transistors Tr.1 and Tr.2 are connected to the bit lines BL0, *BL0 and I/O gate transistors Tr.3 and Tr.4 are connected to the bit lines BL1, *BL1, respectively. Similarly, I/O gate transistors Tr.2i+1 and Tr.2i+2 are connected to the bit lines BLi, *BLi, where i=0 to n+1. When any pair of the I/O gate transistors Tr.1 to Tr.2n+4 turns on, a corresponding bit line pair is connected to an I/O line pair which is an internal data transmission line pair.
In FIG. 3, 2 bits of columns are selected at the same time, so that two pairs of internal data transmission lines I/O0, *I/O0 and I/O1, *I/O1, are disposed. The bit line pairs BL2i, *BL2i of even numbers are connected to the internal data transmission line pairs I/O0, *I/O0, and the bit line pairs of odd numbers BL2i+1, *BL2i+1 are connected to the internal data transmission line pair I/O1, *I/O1. A column selecting operation of the circuit shown in FIG. 3 will now be described.
A column select signal Y0 from the decoder circuit 8-0 is supplied to the gates of the I/O gate transistors Tr.1 and Tr.2 and the gates of the I/O gate transistors Tr.3 and Tr.4. Similarly, the column select signal Y1 from the decoder circuit 8-1 is supplied to each gate of the I/O gate transistors Tr.5 to Tr.8. A column select signal Ym from a decoder circuit 8-m is supplied to each gate of I/O gate transistors Tr.2n+1 to Tr.2n+4.
The column decoder 5 receives an internal column address CA from the column address buffer 4 (see FIG. 1). Each of the decoder circuits 8-0 to 8-m generates a column select signal only when this internal column address bits form a predetermined pattern. One decoder circuit is selected in accordance with a combination of the bits of this internal column address CA. The column select signal of the selected decoder circuit rises to an "H" of the active state, and the column select signals from remaining decoder circuits are maintained at "L" of an inactive state.
Now, suppose that the decoder circuit 8-0 is selected by the internal column address CA and the column select signal Y0 rises to "H". At this time, the I/O gate transistors Tr.1 to Tr.4 are brought to an on-state, and the bit line pairs BL0, *BL0, and BL1, *BL1 are connected to the internal data transmission line pairs I/O0, *I/O0 and I/O1, *I/O1, respectively.
At the time of data reading, data on each of the internal data transmission line pairs I/O0, *I/O0, and I/O1, *I/O1 is sensed and amplified by a sense amplifier (not shown) and then transmitted to the input/output circuit 7.
At the time of data writing, write data from the input/output circuit 7 is transmitted onto the corresponding bit line pairs BL0, *BL0, and BL1, *BL1 over the internal data transmission line pairs.
When the decoder circuit 8-1 is selected by an internal column address CA, the column select signal Y1 rises to "H". At this time, the bit line pairs BL2 *BL2 and BL3, *BL3 are connected to the internal data transmission line pairs I/O0, *I/O0, I/O1, *I/O1 through the I/O gate transistors Tr.5, TR.6, and Tr.7, Tr.8. Input/output of data can be thereby done between the selected two columns, i.e., two bit line pairs BL2, *BL2, and BL3, *BL3 and the internal data transmission line pairs I/O0, *I/O0, and I/O1, *I/O1.
Similarly, when the decoder circuit 8-m is selected in accordance with the internal column address CA, the column select signal Ym rises to "H". In this case, the I/O gate transistors Tr.2n+1 to Tr.2n+4 are brought to the on-state, and input/output of data can be done between the bit line pairs BLn, *BLn, and BLn+1, *BLn+1 and the internal data transmission line pairs I/O0, *I/O0 and I/O1, *I/O1.
In this case, at the time of selecting a column, that is when a column select signal Yj (j=0 to m) rises to "H", a word line has been already selected by the output of the row decoder, so that input/output of data can be done for a memory cell located at a crossing of the selected word line and the selected column.
In accordance with the structure as stated above, arbitrary two columns can be connected to the internal data transmission line pairs by externally supplying a column address, and input/output of data of 2 bits can be performed at the same time.
Generally, as the capacity of a semiconductor memory device becomes larger, the possibility becomes high that defective bits (defective memory cells) will exist in the memory cell array. When a semiconductor memory device in which such defective bits exist is disposed of as a defective product, the product yield of the semiconductor memory device is decreased. Accordingly, there is proposed a structure in which a redundant memory cell array is provided extra to the memory cell array, and if there is a defective bit, the defective bit is equivalently repaired by substituting a redundant row or a redundant column in the redundant memory cell array for a row or a column where this defective bit exists (hereinafter referred to as defective row or defective column).
FIG. 4 is a diagram schematically showing the whole structure of a semiconductor memory device having a conventional redundant structure for repairing a defective bit.
In FIG. 4, the conventional semiconductor memory device having a function of repairing a defective bit includes, in addition to a memory cell array 10, a redundant row memory cell array 10 for repairing a defective row and a redundant column memory cell array 11 for repairing a defective column. The redundant row memory cell array 10 and the redundant column memory cell array 11 respectively include an array of memory cells arranged in a matrix of rows and columns so that a plurality of rows and columns can be repaired.
In order to repair a defective row, there are provided a defective row program circuit 12 for storing the address of the defective row and a spare row decoder 3b for supplying a spare row select (redundant row activation) signal SXD in response to an internal row address from a row address buffer 2 and a defective row address from the defective row program circuit 12.
In order to repair a defective column, there are provided a defective column program circuit 13 for storing the address of the defective column and a spare column decoder 5b for generating a redundant column activation signal SYD in response to an internal column address from a column address buffer 4 and a defective column address from the defective column program circuit 13.
There are provided a row address buffer 2, a normal row decoder 3a, and a column address buffer 4, a normal column decoder 5a in order to select a row and a column of the memory cell array 1 in accordance with an external row address and an external column address.
The defective row program circuit 12 and the defective column program circuit 13 respectively include a laser fusable link element such as a fuse element, and a programming of a defective row or a defective column address is performed by selectively blowing off this link element with a laser beam.
The spare row decoder 3b compares an internal row address from the row address buffer 2 with a defective row address programmed in the defective row program circuit 12. When coincidence is found, it generates a redundant row activation signal SXD and selects a redundant row in the redundant row memory cell array 10. At this time, the spare row decoder 3b supplies a normal element disable signal NED to the normal row decoder 3a to deactivate the normal row decoder 3a and inhibits the row selection in the memory cell array 1.
The spare column decoder 5b compares a defective column address stored in the defective column program circuit 13 with an internal column address from the column address buffer 4, and when they coincide with each other, it generates a redundant column activation signal SYD, supplies the same to the redundant column memory cell array 11 and selects a corresponding column. At this time, the spare column decoder 5b also generates a normal element disable signal NED, supplies the same to the normal column decoder 5a and inhibits the column selecting operation by the normal column decoder 5a. An operation of repairing a defective bit in the semiconductor memory device shown in FIG. 4 will be briefly described in the following.
After the semiconductor memory device has been manufactured, a test is conducted to see if this semiconductor memory device functions normally. In this test, if a determination is made that there is a defective bit in the semiconductor memory device, the address of a row or a column including the defective bit is programmed in the defective row program circuit 12 or the defective column program circuit 13 by blowing off a link element with a laser beam and the like.
If externally applied row address and column address select a row and a column which do not include any defective bit, selection of a row and a column in the memory cell array 1 are conducted respectively by the normal row decoder 3a and the normal column decoder 5a. Subsequently, the selected memory cell (the memory cell located at the crossing of the selected row and the selected column) is connected to the input/output circuit 7 through the (sense amplifier+I/O) block 6.
The internal row address and the internal column address respectively received from the row address buffer 2 and the column address buffer 4 are different from the defective row address and the defective column address stored respectively in the defective row program circuit 12 and the defective column program circuit 13, so that the spare row decoder 3b and the spare column decoder 5b both maintain the inactive state.
An operation when an externally applied row address designates a defective row in the memory cell array 1 will now be described. The internal row address from the row address buffer 2 is supplied to the normal row decoder 3a and the spare row decoder 3b. The spare row decoder 3b compares this internal row address with the defective row address stored in the defective row program circuit 12. At this time, as they coincide with each other, the spare row decoder 3b selects a redundant row in the redundant row memory cell array 10, generates a redundant row activation signal SXD and causes a corresponding redundant row to be in a selected state.
Simultaneously, the spare row decoder 3b generates a normal element disable signal NED and supplies the same to the normal row decoder 3a. While the normal row decoder 3a receives an internal row address from the row address buffer 2, the decoding operation is inhibited by this normal element disable signal NED. Accordingly, selection of the defective row in the memory cell array 1 is inhibited.
The normal column decoder 5a decodes the internal column address which designates a normal column from the column address buffer 4 and generates a signal for selecting a corresponding column. The spare column decoder 5b remains in the inactive state as the internal column address is designating the normal column. Accordingly, in this case, a memory cell is selected, which is located at a crossing of a redundant row in the redundant row memory cell array 10 and a column selected by the column select signal from the normal column decoder 5a, and the selected memory cell is connected to the input/output circuit 7 through the block 6.
With the above-mentioned operation, the defective row in the memory cell array 1 is replaced with the redundant row in the redundant row memory cell array 10, so that the defective bit in the memory cell array 1 is equivalently repaired and writing/reading of data is effected accurately.
An operation when an externally applied column address designates a defective column in the memory cell array 1 will now be described. At this time, in the row selecting circuitry, the normal row decoder 3a is brought to the active state, the spare row decoder 3b is brought to the inactive state, and a row corresponding to the internal row address is selected in the memory cell array 1.
In the column selecting circuitry, the spare column decoder 5b is brought to the active state, generates a column select signal SYD and selects a redundant column corresponding to the defective column stored in the defective column program circuit 13 from the redundant column memory cell array 11. The spare column decoder 5b also, generates a normal element disable signal NED and supplies the same to the normal column decoder 5a. While the normal column decoder 5a receives an internal column address from the column address buffer 4, the decoding operation thereof is inhibited by the normal element disable signal NED from the spare column decoder 5b.
Therefore, in this case, a memory cell of a redundant column connected to a normal row is selected, and the selected memory cell is connected to the input/output circuit 7 through the (sense amplifier+I/O) block 6. The defective column in the memory cell array 1 is thereby replaced with a redundant column in the redundant column memory cell array 11 to repair the defective column.
In the case of the structure of the decoder as shown in FIG. 3, two adjacent pairs of bit lines for example, the bit line pairs BL0, *BL0, and BL1, *BL1, the bit line pairs BL2, *BL2 and BL3 and so on can be, in any case, connected to the internal data transmission line pairs I/O0, *I/O0, and I/O1, *I/O1 at the same time. That is, data of 2 bits can be inputted and outputted at the same time.
In the case of the structure of the decoder as shown in FIG. 3, however, the combination of the bit line pairs selected in response to the external column address is uniquely fixed. For example, when the decoder circuit 8-0 is selected, bit line pairs BL0, *BL0 and BL1, *BL1 are selected at that time. Generally, when a decoder circuit 8-i is selected, bit line pairs BL2i, *BL2i and BL2i+1, *BL2i+1 are selected.
The selected combination of the bit line pairs is determined uniquely in accordance with an external column address. Accordingly, for example, when the combination of the bit line pair BL1, *BL1 and the bit line pair BL2, *BL2 is selected and comparison or operation of data from these two columns is effected, the following procedure is needed. At first, a column address for selecting the decoder circuit 8-0 is inputted, the bit line pairs BL0, *BL0 and BL1, *BL1 are selected, and the data of the bit line pair BL1, *BL1 is held, for example, in an external register. Next, an access is made to the semiconductor memory device to select the decoder circuit 8-1, and the bit line pairs BL2, *BL2 and BL3, *BL3 are selected. Thus, the operation of accessing the semiconductor memory device twice is needed, and there arises a problem that a data processing cannot be conducted at high speed.
Generally, in a structure of a conventional decoder, a combination of target objects (subsequent stage circuits) selected by an externally applied designating signal is uniquely determined, so that there is a problem that an arbitrary combination of target objects cannot be selected at the same time. For example, in detecting if something is wrong with a target object to be controlled and locating a place where there is the abnormality by monitoring outputs of a multiplicity of sensors and interpreting the relationship between the outputs of sensors, when the circuit device for effecting this control operation includes a semiconductor circuit device such as a microcomputer and includes a control operation effecting unit in which a combination of sensor designating signals or selected sensors is determined uniquely, the same problem arises, and there also arises a problem that it is impossible to detect if there is an abnormality in the target object and locate a place where there is the abnormality at high speed.
In a conventional semiconductor memory device, when a redundant structure is employed, repairing of a defective bit can be effected and the product yield of the semiconductor memory devices can be improved. In the structure shown in FIG. 4, however, the decoding operation of the normal row decoder and the normal column decoder is inhibited by a normal element disable signal NED generated from the spare row decoder and the spare column decoder. For this reason, there arises a problem that access cannot be made at high speed. This situation will be more specifically described with reference to the drawings.
FIG. 5 is a diagram schematically showing the structure of a unit decoder circuit included in the normal column decoder shown in FIG. 4. In FIG. 5, the unit decoder circuit includes a gate circuit G1 for receiving a predetermined combination of bits of internal column address CA, *CA from the column address buffer 4 at its true inputs and receiving a normal element disable signal NED at its false input, and an inverter circuit G2 for receiving the output of the gate circuit G1. A column select signal Y is generated from the inverter circuit G2 and applied to the gates of the I/O gate transistors TrI, Tr'I.
In FIG. 5, the case in which a pair of bit lines is selected by the unit decoder circuit is shown as an example. However, a plurality of pairs of bit lines may be selected similarly, and in that case, a column select signal Y is applied to the gates of the I/O gate transistors of adjacent bit line pairs.
The internal column address CA, *CA includes a plurality of bits, and the gate circuits G1 receives a predetermined combination of bits in the internal column address of the plurality of bits. The gate circuit G1 supplies a signal Y, of "L" when a combination of the bits of the internal column address CA, *CA set therein coincides with a predetermined combination of bits, and the normal element disable signal NED attains "L". The operation of the decoder circuit shown in FIG. 5 will now be described referring to FIG. 6 which is a waveform diagram of the operation.
In the case of the semiconductor memory device shown in FIG. 4, a column address and a row address are externally applied in parallel at the same time. The strobe timing of the row address and the column address is determined by a chip select signal CS. When the chip select signal CS (not shown in FIG. 4) rises to "H", an external column address Add which has been supplied to the column address buffer 4 is applied to the inside of the device and supplied to the normal column decoder 5a and the spare column decoder 5b.
The normal column decoder 5a performs a decoding operation in response to the internal column address from the column address buffer 4. When an internal column address of a combination predetermined bits is supplied to the gate circuit G1, the output signal Y' of the gate circuit G1 falls to "L", and accordingly, the column select signal Y from the inverter circuit G2 rises to "H".
Simultaneously, a comparing operation of a defective column address from the defective column program circuit 13 and the internal column address CA, *CA is carried out in the spare column decoder 5b. When coincidence is detected in the spare column decoder 5b, a signal SYD for selecting a redundant column is generated, and at the same time, a normal element disable signal NED is generated.
Accordingly, there is a certain period of time T in which the comparing operation is conducted and the decoding operation is completed in the spare column decoder 5b before the normal element disable signal NED rises to "H" after the chip select signal CS rises to "H".
In this period T, the decoding operation has been already conducted in the normal column decoder 5a, so that the column select signal Y rises to "H" and the defective column is connected to the internal data transmission line pair I/O, *I/O in that period.
When the signal NED rises to "H", the output of the gate circuit G1 rises to "H", the column select signal Y falls to "L", and selection of a defective column is inhibited. A selecting operation of a redundant column is conducted under this situation, so that the redundant column can be connected to the internal data transmission line pair I/O, *I/O.
As described above, on selecting a defective column, data of a defective memory cell is read to the internal data transmission line pair I/O, *I/O since the defective column is connected to the internal data transmission line pair I/O, *I/O in the period T. In order to avoid this, it is necessary to connect the redundant column to the input/output circuit 7 after selection of a defective bit is inhibited and replacement by the redundant column is conducted without fail. Therefore, there is a problem that an access time of semiconductor memory device is made longer due to this period T.
Particularly, as this signal NED is supplied in common to each of decoder circuits of the column decoder, to time period in which the signal NED reaches a decoder circuit most distant from the spare column decoder 5b is the longest. As it is necessary to set a write/read timing of the data taking account of the time period in which the signal NED reaches the decoder circuit in the most distant place, there arises a problem that an access to the semiconductor memory device is further delayed.
This operation is conducted in a similar way in the row selecting circuitry, and when the spare row decoder 3b is activated and the spare row select signal SXD is generated, the normal element disable signal NED is supplied to the normal row decoder 3a and the row selecting operation is inhibited. Therefore, it is necessary to effect a selecting operation of a bit line after a time period has passed in which the defective row is once brought to a selected state. Similarly, the time required for the row selecting operation is made longer, making the access time longer.
There is also a case in which a structure of a normal decoder as shown in FIG. 7 is employed in place of the structure where the decoder circuit is brought to the inactive state by using the signal NED as described above.
FIG. 7 is a diagram showing another structure of a unit decoder circuit contained in a conventional normal column decoder. In FIG. 7, the unit decoder circuit includes a gate circuit G10 for decoding an internal column address CA, *CA, and a column select signal generating circuit LA having a function of bringing a bit line pair to a non-selected state in any case when the bit line pair BL0, *BL0 is a defective column as well as receiving the output of the gate circuit G10 through a link element LE and driving a column select signal Y.
The gate circuit G10 supplies a signal of "L" when the internal column address CA, *CA includes a plurality of bits of a predetermined combination. The link element LE is laser fusable and blown off, for example, with a laser beam when a column (bit line pair BL0, *BL0) selected by the gate circuit G10 is a defective column, and to disconnect the output of the gate circuit G10 and the bit line pair BL0, *BL0.
The column select signal generating circuit LA includes a P channel MOS transistor (insulated gate type field effect transistor) TP1 and an N channel MOS transistor TN1 constituting an inverter for inverting the output of the gate circuit G10 and P channel MOS transistors TP2 and TP3 constituting a latch circuit for initializing the output signal line of the column select signal generating circuit LA to "L" when the power supply is turned on.
The P channel MOS transistor TP2 receives the output signal of the inverter (transistors TP1 and TN1) at the gate. The P channel MOS transistor TP3 receives at the gate a power-on detecting signal *POP which is brought to "L" for a predetermined period of time when the power supply is turned on. The transistors TP2 and TP3 are connected in parallel with each other, and have conduction terminals connected in common to the power supply Vcc, and another conduction terminals of them connected in common to the gates of the transistors TP1 and TN1. The operation of the decoder circuit shown in FIG. 7 will now be described.
When the bit line pair BL0, *BL0 is a normal column, the link element LE is in a conductive state. When the power supply is turned on, the signal *POP is brought to "L" for a predetermined period of time. Responsively to this, the transistor TP3 is brought to the on-state and the power supply potential Vcc is supplied to the gates of the transistors TP1 and TN1. The transistor TN1 is brought to the on-state in response to the transmitted power supply potential Vcc, and the column select signal Y is set to "L" of the ground potential. Even if the signal *POP rises to "H" after a predetermined period of time has passed, the column select signal Y is at "L", so that the transistor TP2 is brought to the on-state, keeping the transistor TN1 in the on-state and the transistor TP1 in an off-state.
When the gate circuit G10 is selected by the internal column address CA, *CA, the gate circuit G10 supplies a signal of "L". At this time, the transistor TP1 is brought to the on-stage, the transistor TN1 is brought to the off-stage, the column select signal Y rises to "H" and the bit line pair BL0, *BL0 is connected to the internal data transmission line pair I/O0, *I/O0 through the transistors Tr0, Tr0'. Selection of a normal column is thereby completed. In this case, the current drive capability of the transistor TP2 is smaller than the current drive capability of the gate circuit G10, so that an on/off operation of the transistors TP1 and TN1 is effected in accordance with the output of the gate circuit G10, regardless of the on-state of the transistor TP2. When the column select signal Y rises to "H", the transistor TP2 is brought to the off-state, so that the column select signal Y is raised to "H" at high speed.
When the bit line pair BL0, *BL0, to which the decoder circuit including the gate circuit G10 is connected, the defective column, the link element LE is blown off with a laser beam and the like. As a result, the gate circuit G10 is disconnected from the bit line pair BL0, *BL0.
When the power supply is turned on, the transistor TP3 causes the transistor TN1 to be in the on-state and causes the column select signal Y to fall to "L". The transistor TP2 is brought to the on-state in response to this "L" column select signal Y, setting the column select signal Y to "L" all the time. Selection of a defective column is thereby inhibited.
In the case of the structure of the decoder circuit using a link element as described above, it is necessary to provide a link element LE for each decoder circuit. When the capacity of a semiconductor memory device becomes larger, it will be necessary to arrange a multiplicity of memory cells in a limited area, so that a bit line pitch will be smaller. It is necessary to form a decoder circuit in accordance with this bit line pitch and locate a link element in accordance with this small bit line pitch.
The link element is blown off with a laser beam. A pitch larger than the bit line pitch is required for the link element, in order to prevent adverse effects on adjacent signal lines (short circuiting of the signal line due to splashes of the melted pieces) caused by the portion blown off at the time of laser fusing. Accordingly, when a bit line pitch is made smaller as the capacity of the semiconductor memory device becomes larger, there arises a problem that it is difficult to provide a link element for each bit line pair.
A structure is employed in place of the memory cell array structure shown in FIG. 4, in which a memory cell array is divided into a plurality of blocks in a mass storage semiconductor memory device and a selecting operation of a row and column is effected for each block.
FIG. 8 is a diagram schematically showing the overall structure of a still another conventional semiconductor memory device. In FIG. 8, the semiconductor memory device includes four divided memory cell array blocks 1a, 1b, 1c and 1d. Each of the memory cell array blocks 1a to 1d includes a plurality of memory cells arranged in rows and columns.
There are provided normal row decoders 30a to 30d, spare row decoders 31a to 31d, redundant row memory cell arrays 10a to 10d and (sense amplifier+I/O) blocks 6a to 6d, corresponding to each of the memory cell array blocks 1a to 1d. An internal row address from the row address buffer 2 is supplied in parallel to each of the normal row decoders 30a to 30d and the spare row decoders 31a to 31d. One row is selected in each of the memory cell array blocks 1a to 1d.
Redundant column memory cell arrays 11a to 11d for repairing a defective column are provided in the memory cell array blocks 1a to 1d.
In order to select a column from each of the memory cell array blocks 1a to 1d, there are provided a column address buffer 4 for receiving an external column address and generating an internal column address, a normal column decoder 5a and a spare column decoder 5b for decoding the internal column address. The normal column decoder 5a is provided in common for the memory cell array blocks 1a to 1d, and the spare column decoder 5b is also provided in common for each of the redundant columns 11a to 11d.
An input/output circuit 7a is provided for selectively effecting input/output of data with the memory cell array blocks 1a and 1b and an input/output circuit 7b is provided for selectively effecting input/output of data with the memory cell array blocks 1c and 1d. An input/output circuit 7c is provided for selectively effecting input/output of data with the input/output circuits 7a and 7b.
Selection of an input/output column in the input/output circuits 7a, 7b and 7c is effected, for example, by decoding a block address to select a block with the most significant row address bit and the most significant column address bit being as the block address in the input/output circuit 7c.
In such a semiconductor memory device, redundant row memory cell arrays 10a to 10d are provided for each of the memory cell array blocks 1a to 1d, and spare row decoders 31a to 31d are provided correspondingly. Accordingly, repairing of a defective row can be effected independently in each of the memory cell array blocks 1a to 1d.
While the redundant column memory cell arrays 11a to 11d are provided respectively corresponding to the memory cell array blocks 1a to 1d, the spare column decoder 5b is provided in common to the redundant column memory cell arrays 11a to 11d. Accordingly, repairing of a defective column is effected in common to each block. That is, replacement with a redundant column is effected in each block regardless of the presence/absence of a defective column in the block. Therefore, for example, when a redundant column in the redundant column memory cell array 11a is used for repairing the defective column in the memory cell array block 1a, a corresponding redundant column is also used in each of the redundant column memory cell arrays 11b to 11d so that there arises a problem that each block cannot utilize the redundant columns independently and repairing of the defective column cannot be performed effectively.